Dynamic Random Access Memory (DRAM) is used in modern computing architectures. DRAM may provide advantages of structural simplicity, low cost, and speed in comparison to other types of memory.
Presently, DRAM commonly has individual memory cells that have one capacitor in combination with a field effect transistor (so-called 1T-1C memory cells), with the capacitor being coupled with one of the source/drain regions of the transistor. One of the limitations to scalability of present 1T-1C configurations is that it is difficult to incorporate capacitors having sufficiently high capacitance into highly-integrated architectures. Accordingly, it would be desirable to develop new memory cell configurations suitable for incorporation into highly-integrated modern memory architectures.
While the invention was motivated by architecture and method associated with other than 1T-1C memory cells, some aspects of the invention are in no way so limited and may have applicability to any memory cell and to methods used in fabricating any integrated circuitry.